1. Field of the Invention
The present invention relates to a data write circuit and data write method for a semiconductor storage device such as EEPROM.
2. Description of the Related Art
A conventional EEPROM has employed a single bit write method in which each write operation (holding of a single write operation) performs data writing to one memory cell (single bit). However, recent increase in memory capacities arouses concern about an increase of the time period for such data writing. In order to avoid this concern, a multi-bit write method is employed in which each write operation (holding of a single write operation) performs data writing to a plurality of memory cells (multi-bits).
FIG. 7 shows a block diagram of a conventional EEPROM. The conventional EEPROM in FIG. 7 includes a memory cell array having a plurality of memory cells arranged in a matrix pattern, a conventional data write circuit for data writing to the memory cells in the memory cell array, an input pad 1 for receiving data DQ to be written to the memory cells, three input pads 2 for respectively receiving 3 configuration bits MA0, MA1 and MA2 as a multi-bit addresses MBA, an input pad 3 for receiving the address ADD formed by a column address and a row address, an input pad 15 for receiving a write voltage VPP, an input pad 16 for receiving a control signal CEB, and an input pad 17 for receiving a control signal OEB.
Referring to FIG. 7, the conventional data write circuit mentioned above further includes eight multi-bit decoder & data latch circuits 4 (4-A0, 4-A1, . . . 4-A7) for decoding the multi-bit address MBA and latching the input data DQ, eight column decoders 5 (5-A0, 5-A1, . . . 5-A7) for decoding the column address, a row decoder 6 for decoding the row address, and a cell drain voltage generator 7. Accordingly, multi-bit writing can be achieved to the memory cells consisting of eight multi-bits A0, A1, . . . A7. The multi bit decoder & data latch circuit 4-Ak and column decoder 5-Ak are in charge of the multi-bit Ak, where k denotes an arbitrary integer from 0 to 7.
FIG. 8 shows an example of a logic circuit diagram in the cell drain generator 7 of the conventional data write circuit of FIG. 7. This conventional cell drain voltage generator 7 includes a high voltage detection circuit 30 for outputting a write voltage detection signal VPPH which becomes L level when the write voltage VPP to be input is at low voltage level (e.g. GND level (0 volt)), and becomes H level when the write voltage VPP is at high voltage level (e.g. 8 volts). The circuit of the cell drain voltage generator 7 outputs a cell drain voltage CDV of either 0.6 volts or 5.0 volts depending on the logic of the write voltage detection signal VPPH and the control signals CEB and OEB.
FIG. 9 shows a timing chart of conventional multi-bit writing for the EEPROM of FIG. 7. Before time t1, the row decoder 6 sets all of M word lines WL1 to WLM and two select lines SLodd and SLeven to GND level (0 volt). All the multi-bit decoder & data latch circuits 4-A0 to 4-A7 latch H level as the initial data, and latch inputs of these multi-bit decoder & data latch circuits 4-A0 to 4-A7 are all disconnected from the input pad 1.
Then at time t1, the multi-bit address MBA for selecting the multi-bit A0 is input from the input pad 2. Further, in the case of an example of FIG. 9, the address ADD for selecting a decode address a0 of the word line WLm, odd select line SLodd and the bit lines BLn-A0 to BLn-A7 is input from the input pad 3.
Moreover, at time t1, the write voltage detection signal VPPH (write voltage VPP) and the control signals CEB and OEB are VPPH (VPP)/CEB/OEB=H level (high voltage level (approx. 8.0 volts)/H level/H level, and in the cell drain voltage generator 7 (see FIG. 8), the output of the NAND gate 33 is H level and the output of the NAND gate 34 is L level, and thus the PMOS transistor 31 is OFF and the PMOS transistor 32 is ON so that a cell drain voltage CDV of approx. 0.6 volts is output from the cell drain voltage generator 7.
When the row address among the address ADD for selecting the decode address a0 is input, the row decoder 6 selects the word line WLm from M word lines WL1 to WLM, and selects the odd select line SLodd from two select lines SLodd and SLeven, and applies approx. 8.0 volts from the write voltage VPP to the word line WLm and the odd select line SLodd. Upon this voltage application, all the odd selectors (including odd selectors 8-odd1 and 8-odd2) turn ON so that the cell drain voltage CDV (approx. 0.6 V in this case) is supplied to all the drain lines (including drain lines DLodd1 and DLodd2) connected to these odd selectors.
When the column address among the address ADD for selecting the decode address a0 is input, the column decoder 5-Ak in charge of the multi-bit Ak selects the bit line BLn-Ak, and connects the output of the multi-bit decoder & data latch circuit 4-Ak in charge of the multi-bit Ak to this bit line BLn-Ak.
When the multi-bit address MBA for selecting the multi-bit A0 is input, the multi-bit decoder & data latch circuit 4-A0 in charge of the multi-bit A0 connects the latch input to the input pad 1.
Then at time t2, the control signal CEB to be input to the cell drain voltage generator 7 from the input pad 16 changes from H level to L level, and the write disabled period changes to the write operation period.
As described above, when the logic changes from VPPH (VPP)/CEB/OEB=H level (high voltage level)/H level/H level to VPPH (VPP)/CEB/OEB=H level (high voltage level)/L level/H level and the write disabled period changes to the write operation period, the output of the NAND gate 33 in the cell drain voltage generator 7 (see FIG. 8) changes from H level to L level and the output of the NAND gate 34 changes from L level to H level, and thus the PMOS transistor 31 turns ON and the PMOS transistor 32 turns OFF so that the cell drain voltage CDV to be output from the cell drain voltage generator 7 rises from approx. 0.6 volts to approx. 5.0 volts.
This cell drain voltage CDV with a high voltage level (approx. 5.0 volts) is supplied to the drains of half the memory cells out of all the memory cells of the memory cell unit via all the odd selectors (including odd selectors 8-odd1 and 8-odd2) and all the drain lines (including drain lines DLodd1 and DLodd2).
In the case of a memory cell where approx. 8.0 volts is applied to the control gate from the word line WLm and the source is connected to the latch output of the multi-bit decoder & data latch circuit 4-Ak via the bit line BLn-Ak and column decoder 5-Ak, rise of the cell drain voltage CVD applied to the drain to approx. 5.0 volts causes an electron injection into the floating gate if the latch data of the multi-bit decoder & data latch circuit 4-Ak is at L level and the voltage to be applied from the bit line BLn-Ak to the source is GND level (0 volt). On the other hand, the rise of the cell drain voltage CVD to approx. 5.0 volts causes no electron injection into the floating gate if the latch data of the multi-bit decoder & data latch circuit 4-Ak is at H level and the voltage to be applied from the bit line BLn-Ak to the source is close to the power supply voltage VCC (approx. 3.5 volts).
In other words, if the cell drain voltage CDV rises to approx. 5.0 volts, the input data DQ-Ak that is latched by the multi-bit decoder & data latch circuit 4-Ak can be written to the memory cell of the multi-bits Ak selected by the word line WLm and the bit line BLn-Ak.
During this data write period, the multi-bit addresses MBA to select the multi-bits A0 to A7 are sequentially input from the input pad 2, and eight data of DQ-A0 to DQ-A7 to be respectively written to the eight multi-bits A0 to A7 are sequentially input from the input pad 1. Then, these input data DQ-A0 to DQ-A7 are latched by the multi-bit decoder & data latch circuits 4-A0 to 4-A7 in charge of the multi-bits A0 to A7, respectively. Accordingly, these input data DQ-A0 to DQ-A7 are written to the memory cells of the multi-bits A0 to A7, respectively.
When the data DQ-A0, which is either at H level or L level, to be written to the memory cell 9 of the multi-bit A0 is input from the input pad 1, the multi-bit decoder & data latch circuit 4-A0 in charge of the multi-bit A0, which is being selected at this time, latches the input data DQ-A0 instead of the initial data (H level). The input data DQ-A0 latched by the multi-bit decoder & data latch circuit 4-A0 is output to the bit line BLn-A0 via the column decoder 5-A0, and is written to the memory cell 9 of the multi-bit A0.
If the data DQ-A0 is L level, the source of the memory cell 9 becomes GND level (0 volt), and thus electrons are injected into the floating gate of the memory cell 9, whereas if the data DQ-A0 is H level, the source of the memory cell 9 becomes close to the power supply voltage VCC (approx. 3.5 volts), and thus no electron is injected into the floating gate of the memory cell 9.
Then at time t3, when the multi-bit address MBA to be input from the input pad 2 is changed from a value for selecting the multi-bit A0 to a value for selecting the multi-bit A1, the multi-bit decoder & data latch circuit 4-A0 in charge of the multi-bit A0 disconnects the latch input from the input pad 1, and the multi-bit decoder & data latch circuit 4-A1 in charge of the multi-bit A1 connects the latch input to the input pad 1.
Then, when the data DQ-A1 to be written to the memory cell 10 of the multi-bi A1 is input from the input pad 1, the multi-bit decoder & data latch circuit 4-A1 in charge of the multi-bit A1, which is being selected at this time, latches the input data DQ-A1 instead of the initial data (H level). This input data DQ-A1 latched by the multi-bit decoder & data latch circuit 4-A1 is output to the bit line BLn-A1 via the column decoder 5-A1, and is written to the memory cell 10 of the multi-bit A1.
In the same way, the multi-bit addresses MBA to be input from the input pad 2 at times t4, t5, t6, t7, t8 and t9 are sequentially changed to values to select the multi-bit A2, the multi-bit A3, the multi-bit A4, the multi-bit A5, the multi-bit A6 and the multi-bit A7, and then the data DQ-A2 to be written to the memory cell of the multi-bit A2, the data DQ-A3 to be written to the memory cell of the multi-bit A3, the data DQ-A4 to be written to the memory cell of the multi-bit A4, the data DQ-A5 to be written to the memory cell of the multi-bit A5, the data DQ-A6 to be written to the memory cell of the multi-bit A6 and the data DQ-A7 to be written to the memory cell of the multi-bit A7 are sequentially input from the input pad 1.
These input data DQ-A2, DQ-A3, DQ-A4, DQ-A5, DQ-A6 and DQ-A7 are sequentially latched by the multi-bit decoder & data latch circuit 4-A2 in charge of the multi-bit A2, the multi-bit decoder & data latch circuit 4-A3 in charge of the multi-bit A3, the multi-bit decoder & data latch circuit 4-A4 in charge of the multi-bit A4, the multi-bit decoder & data latch circuit 4-A5 in charge of the multi-bit A5, the multi-bit decoder & data latch circuit 4-A6 in charge of the multi-bit A6, and the multi-bit decoder & data latch circuit 4-A7 in charge of the multi-bit A7, respectively, and then sequentially written to the memory cells of the multi-bits A2, A3, . . . A7, respectively.
The data write operation of an EEPROM involves the electron injection into the floating gate of the memory cell, the write operation must be held for a long time (approx. 10 microseconds (μs) in FIG. 9) until the electron injection is completed, and the data writing of eight memory cells of the multi-bits A0 to A7 is completed by holding the write operation for approx. 10 μs from the data writing of the memory cell selected last, i.e., the multi-bit A7. During the above-described data writing period, the time required for inputting data DQ-A0 to DQ-A7 is approx. 350 nanoseconds in FIG. 9, which is very short as compared with the holding period for write operation of the above-mentioned approx. 10 μs.
As described above, in the case of a multi-bit write method, data are written to a plurality of memory cells during a long holding period of one write operation.
In a single bit write method, on the other hand, data is written to one memory cell during a long single holding period of one write operation (e.g. Japanese Patent Application Kokai No. 2000-331486 (FIG. 1, FIG. 3)).
FIG. 10 shows a timing chart of a conventional single bit writing for the EEPROM of FIG. 7, where the same reference numerals are assigned for the same elements as FIG. 9. Noted that in the above-described multi-bit writing, the data are written into eight memory cells of the multi-bits A0 to A7 within a single writing operation, and the address ADD covers the above-described multi-bits. In a single bit writing, on the other hand, the data is written into one memory cell within a single writing operation, and therefore the address ADD and the multi-bit address MBA cover only the above-described one memory cell. Accordingly, as shown in FIG. 10, the decode address a0 and the multi-bits A0, A1, A2, A3, . . . during the multi-bit writing constitute the decode addresses for the single bit writing such as a0+A0, a0+A1, a0+A2, a0+A3 and so on. As shown in FIG. 10, although each write operation has the same address ADD, i.e., all decode addresses are a0, each write operation, i.e., each memory cell, may has different address ADD in the single bit writing.
Before time t21, the row decoder 6 sets all M word lines WL1 to WLM and the two select lines SLodd and SLeven to GND level (0 volt). The multi-bit decoder & data latch circuits 4-A0 to 4-A7 all latch the H level as the initial data, and the latch inputs of these multi-bit decoder & data latch circuits 4-A0 to 4-A7 are all disconnected from the input pad 1.
At time t21, the address ADD and the multi-bit address MBA to select the decode address a0+A0 are input from the input pads 2 and 3.
When the row address among the address ADD to select the decode address a0 is input, the row decoder 6 selects the word line WLm and the odd select line SLodd, and applies approx. an 8.0 volts from the write voltage VPP to the word line WLm and the odd select line SLodd. Upon this voltage application, all the odd selectors turn ON so that the cell drain voltage CDV (approx. 0.6 volts in this case) is supplied to all the drain lines connected to these odd selectors.
When the column address among the address ADD to select the decode address a0 is input, the column decoder 5-Ak selects the bit line BLn-Ak, and connects the output of the multi-bit decoder & data latch circuit 4-Ak to this bit line BLn-Ak.
When the multi-bit address MBA to select the multi-bit A0 is input, the multi-bit decoder & data latch circuit 4-A0 connects the latch input to the input pad 1.
Then at time t22, the control signal CEB to be input to the cell drain voltage generator 7 from the input pad 16 changes from H level to L level, and then the write disabled period changes to the write operation period.
As described above, when the write disabled period changes to the write operation period, the cell drain voltage CDV to be output from the cell drain voltage generator 7 (see FIG. 8) rises from approx. 0.6 volts to approx. 5.0 volts.
When the cell drain voltage CDV rises to approx. 5.0 volts, the input data DQ-A0 latched by the multi-bit decoder & data latch circuit 4-A0 can be written to the memory cell 9 of the decode address a0+A0 selected by the word line WLm and the bit line BLn-A0.
During this write operation period, the data DQ-A0 is input from the input pad 1, and this input data DQ-A0 is latched by the multi-bit decoder & data latch circuit 4-A0, and is written to the memory call 9 of the decode address a0+A0. Holding of the write operation for approx. 10 μs from the start of the input of the data DQ completes the data writing.
When at time t23, that is after the holding of the write operation for approx. 10 μs, the control signal CEB to be input to the cell drain voltage generator 7 from the input pad 16 changes from L level to H level, and the write operation period ends so as to return to the write disabled period.
As described above, when the write operation period changes to the write disabled period, the cell drain voltage CDV to be output from the cell drain voltage generator 7 (see FIG. 8) falls from approx. 5.0 volts to approx. 0.6 volts.
Then at time t24, when the address ADD and the multi-bit address MBA input from the input pads 2 and 3 are changed from the values to select the decode address a0+A0 to the values to select the decode address a0+A1, the input data DQ-A1 is latched by the multi-bit decoder & data latch circuit 4-A1 and is written to the memory cell 10 of the decode address a0+A1 during t24 to t27, which are similar to those during t21 to t24 described above.
In the same way, the input data DQ-A2, DQ-A3 . . . are latched by the multi-bit decoder & data latch circuits 4-A2, 4-A3, . . . , and are written to the memory cells of the decode addresses a0+A2, a0+A3, . . . , during t27 to t30, . . . , respectively.
Accordingly, in the single bit write method, a specified time (approx. 10 μs in FIG. 10) multiplied by the number of all memory cells to which the data is written is required to hold the write operation. On the other hand, in the multi-bit write method, a specified time (approx. 10 μs in FIG. 9) multiplied by only ⅛ (1/the number of multi-bits) of the number used in the single bit write method described above is enough. Therefore if the data input cycle time in one multi-bit writing can be executed in several tens nanoseconds (approx. 350/8 nanoseconds in FIG. 9), then overall time required for writing all the memory cells by the multi-bit write method is approx. ⅛ (1/the number of multi-bits) of that of the single bit write method. Accordingly, the multi-bit write method offers advantage over the single bit write method.
This advantage of the multi-bit write method can be utilized for a memory tester etc. having capability to control a high-speed data input cycle (several tens nanoseconds or less), but a ROM writer for data writing used by a conventional ROM user cannot utilize the advantage of the multi-bit write method, since the data input cycle that can be controlled is limited to 4 to 5 μs.
If the multi-bit write method is executed in the ROM writer, it takes several tens μs to merely input data of all the multi-bits, which far exceeds the holding period for the write operation (approx. 10 μs in FIG. 9 and FIG. 10), thereby causing erroneous phenomena in data writing to a non-selected memory cell, i.e., phenomena of electron injection to the floating gate of the non-selected memory cell.
FIG. 11 shows a cross-sectional view of such erroneous phenomena, when L level latch data is written to the memory cell 9 in FIG. 7, in data writing to the non-selected memory cells 11, 12 and 13 having no injected electron connected to the selected word rows. In the floating gate 19 of the memory cell 9 where the GND level (0 volt) is supplied to the source 24 (bit line BLn), electrons have been injected and kept stored owing to the control gate 18 (word line WLm) to which approx. 8.0 volts of voltage is supplied and the drain 23 to which approx. 5.0 volts of cell drain voltage CDV is supplied.
On the other hand, since the cell drain voltage CDV of approx. 5.0 volts is supplied to the drain 25 of the memory cell 13, if the write operation in FIG. 11 is held for several tens μs, electrons may be injected into the floating gates 20, 21 and 22 having no injected electron of the non-selected memory cells 11 to 13, which are located between the source 24 and the drain 25 owing to the control gate 18 to which approx. 8.0 volts of voltage is supplied and the drain 25 to which approx. 5.0 volts of cell drain voltage CDV is supplied.
Because of the above-described reason, the ROM writer that holds the write operation for several tens μs during multi-bit writing employs the single bit write method instead of the multi-bit write method.
However, because of the recent miniaturization of processes and the increase in memory capacities, data retention phenomena in the non-selected cells can no longer be ignored, which poses another problem in a single bit writing method.
FIG. 12 shows a cross-sectional view of such data retention phenomena, when L level latch data is written to the memory cell 9 in FIG. 7, in the non-selected memory cell of the non-selected word row such as memory cell 14 for which electron injection has completed. During the write operation, cell drain voltage CDV (approx. 5.0 volts) is supplied to the drains of half of the entire memory cells by means of the odd selector and the even selector. In a non-selected memory cell where electrons have already been injected into the floating gate 27 and the GND level (0 volt) is supplied to the control gate 26, electrons held in the floating gate 27 jump the oxide film and reach the drain 29, if the cell drain voltage CDV of approx. 5.0 volts is being supplied to the drain 29 for a long time, even if the source 28 is open. Accordingly, such case may be increased that the electrons held in the floating gate 27 flow out to the supply line of the cell drain voltage CDV. As a result, electrons in the floating gate 27 decrease, which makes it difficult to read these memory cells.
This problem is more significant in the single bit writing having longer write operation. Further, this problem cannot be ignored as the oxide film between the floating gate and drain becomes thinner due to the miniaturization of the process, and as the time to apply a high cell drain voltage to non-selected memory cells during write operation becomes longer due to the capacity increase of the memories. As a result, a serious problem arises in that there is no way to write data in the case of a ROM writer where the limit of a data input cycle that can be controlled is 4 to 5 μs and the multi-bit writing cannot be employed.